Duplexer structure for coupling a transmitter and a receiver to a common antenna

ABSTRACT

A duplexer structure for allowing an RF transmitter and an RF receiver to share a common antenna includes impedance matching circuitry to match the receiver input impedance to the antenna impedance during a receive operation and impedance transformation circuitry to transform the antenna impedance to a lower impedance at the receiver input terminals during a transmit operation. The impedance matching circuitry and the impedance transformation circuitry of the duplexer share one or more passive components, thus reducing the overall number of components required to implement the duplexer. This reduction in component count reduces the amount of chip area required to implement the duplexer and increases the ease with which the RF transceiver is integrated onto a semiconductor chip. In one embodiment, the duplexer uses a differential topology to provide common mode noise rejection and even harmonic distortion cancellation within a transceiver.

FIELD OF THE INVENTION

[0001] The invention relates generally to radio frequency transceiversand, more particularly, to transceivers having a transmitter and areceiver that share a common antenna.

BACKGROUND OF THE INVENTION

[0002] It is often desirable to have a radio frequency (RF) transmitterand receiver share a common antenna. This practice reduces the overallcost of implementing an RF system by eliminating one antenna. It alsoensures that the transmit and receive beams of the system are identical.A number of challenges arise, however, in implementing a shared antennaarrangement. For example, during transmit operations, the relativelyhigh transmit power generated by the transmitter cannot be permitted tooverload the front end of the receiver. In addition, during a receiveoperation, the received signal must be directed from the antenna to thereceiver input with little loss in the intervening circuitry.Furthermore, both the transmitter and the receiver must be appropriatelymatched to the antenna during transmit and receive operations,respectively, to enhance power transfer between these elements. Duplexerstructures are normally employed to address these issues.

[0003] An ongoing trend in the electronics industry is to integrateentire systems or subsystems onto a single semiconductor chip using, forexample, very large scale integration (VLSI) techniques. Because of itscharacteristic low power consumption, low cost, and high integrationdensity, complementary metal-oxide-semiconductor (CMOS) technology isoften used to achieve this integration. The integration of RFtransceiver subsystems, however, has thus far presented a majorchallenge to circuit designers. This is because RF transceiverstypically make extensive use of passive components (e.g., inductors andcapacitors) which are not easily implemented on a semiconductor chip.Another reason is because RF transceivers are generally required todetect very small signals from an antenna which can be obscured by, forexample, digital switching noise when the RF circuitry is implemented onthe same chip as digital circuitry performing control and signalprocessing functions for the transceiver. This is especially true for RFtransceiver subsystems that utilize antenna sharing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 is a block diagram illustrating an RF transceiver inaccordance with one embodiment of the present invention;

[0005]FIG. 2 is a block diagram illustrating the internal configurationof a duplexer within the RF transceiver of FIG. 1 in one embodiment ofthe present invention; and

[0006]FIG. 3 is a schematic diagram illustrating a differential duplexercircuit in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

[0007] In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein in connection with one embodiment may beimplemented within other embodiments without departing from the spiritand scope of the invention. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims, appropriately interpreted, alongwith the full range of equivalents to which the claims are entitled. Inthe drawings, like numerals refer to the same or similar functionalitythroughout the several views.

[0008] The present invention relates to a duplexer structure that allowsan RF transmitter and an RF receiver to share a common antenna. Theduplexer includes impedance matching circuitry to match the receiverinput impedance to the antenna impedance during a receive operation andimpedance transformation circuitry to transform the antenna impedance toa lower impedance at the receiver input terminals during a transmitoperation (to protect the receiver from damage). Significantly, theimpedance matching circuitry and the impedance transformation circuitryof the duplexer share one or more passive components. This componentsharing reduces the overall number of passive components within thecorresponding RF transceiver, thus increasing the ease with which the RFtransceiver is integrated onto a semiconductor chip and reducing theamount of chip area required to implement the duplexer. In oneembodiment, the duplexer uses a differential topology to provide commonmode noise rejection and even harmonic distortion cancellation. This isbeneficial when the duplexer is located within a hostile digitalenvironment (e.g., when the duplexer is implemented on the same chipwith digital control circuitry). The differential topology also allowsthe duplexer structure to take advantage of the high integrationcapabilities of CMOS technology.

[0009]FIG. 1 is a block diagram illustrating an RF transceiver 10 inaccordance with one embodiment of the present invention. As shown, areceiver 12 and a transmitter 14 are each coupled to a duplexer 16 thatcommunicates with an external antenna 18. The duplexer 16 includes aninput 20 for receiving a transmit/receive (TX/RX) signal that isindicative of the present operational state of the transceiver. If theTX/RX signal indicates that the transmitter 14 is currently active(i.e., a transmit operation is being performed), the duplexer 16 isconfigured so that the transmitter 14 is appropriately coupled to theantenna 18 to deliver a relatively high power transmit signal thereto.Although the voltage swing at the antenna port 22 will typically berelatively high during the transmit operation, the duplexer 16 isdesigned so that the voltage swing at the input port 24 of the receiver12 remains relatively low during the transmit operation to preventdamage to the front end receiver circuitry. As will be described ingreater detail, this is accomplished by implementing an impedancetransformation within the duplexer 16 that transforms the relativelylarge antenna impedance to a much lower impedance at the input port 24of the receiver 12.

[0010] If the TX/RX signal indicates that a receive operation is beingperformed, the duplexer 16 is configured so that the antenna 18 iscoupled through to the receiver 12 in a relatively low loss manner. Inprevious transceiver designs, the receiver has typically been internallymatched so that an input impedance of the receiver was the same as, orsimilar to, the antenna impedance. Thus, the intervening duplexer inthese designs only needed to provide a through connection atsubstantially the same impedance to generate a low loss connectionbetween the antenna and the receiver during receive mode. In one aspectof the present invention, however, the duplexer 16 includes matchingcircuitry for matching the input impedance of the receiver 12 to theimpedance of the antenna 18 during receive operations, thus reducing oreliminating the need to provide internal matching within the receiver12. In addition, in accordance with one embodiment of the invention,this matching circuitry shares one or more passive components with theimpedance transformation circuitry used during transmit operations. Ascan be appreciated, this component sharing reduces the amount of chipspace required to implement the duplexer and simplifies the integrationprocess.

[0011]FIG. 2 is a block diagram illustrating an internal configurationof the duplexer 16 of FIG. 1 in one embodiment of the present invention.As shown, the duplexer 16 includes a reconfigurable network 28 that isconfigured as an impedance matching network during receive operationsand as an impedance transformation network during transmit operations.In the illustrated embodiment, the input 24 of the receiver 12 isdirectly coupled to the output 32 of the transmitter 14 within theduplexer 16. In another embodiment, as will be described in greaterdetail below, additional switching functionality is provided within theduplexer 16 for isolating the transmitter 14 during receive operations.The network 28 receives the TX/RX signal at input 20 which configuresthe network 28 based on the current operational state of the transceiver10. The impedance transformation of the network 28 during transmitoperations transforms the antenna impedance at the antenna port 22(e.g., 50 ohms) to a relatively low impedance (e.g., 10 ohms) at theinput port 24 of the receiver 12. Thus, although the voltage swing atthe antenna port 22 will typically be relatively high during a transmitoperation to achieve a desired transmission range, the voltage swing atthe input terminal 24 of the receiver 12 will remain low. The impedancetransformation is designed so that the maximum anticipated voltage swingat the antenna port 22 during a transmit operation will require avoltage swing at circuit node 34 (and thus the input port 24 of thereceiver 12) that is below a value that could potentially damage thereceiver front end. The impedance transformation should also provide agood impedance match between the output 32 of the transmitter 14 and theantenna 18.

[0012] As described above, in one embodiment of the present invention,the impedance matching network and the impedance transformation networkimplemented within the duplexer 16 share one or more passive circuitelements. That is, the impedance matching network will use the circuitelement(s) during receive operations and the impedance transformationnetwork will use the circuit element(s) during transmit operations. Byimplementing element sharing within the duplexer 16, the physical sizeof the resulting circuit can be reduced. FIG. 3 is a schematic diagramillustrating a duplexer circuit 40 that employs element sharing inaccordance with one embodiment of the present invention. The duplexercircuit 40 is a differential circuit and thus provides common mode noiseisolation and even mode distortion cancellation. The duplexer circuit 40includes first and second receiver terminals 42, 44 for connection to alow noise amplifier (LNA) 50 that is part of an RF receiver; first andsecond transmitter terminals 46, 48 for connection to a power amplifier(PA) that is part of an RF transmitter; and first and second antennaterminals 56, 58 for connection to an antenna assembly 54. Asillustrated, the antenna assembly 54 includes an optional balun 60 foruse in coupling the balanced antenna terminals 56, 58 to a single-endedantenna structure 62 (if this is the type of antenna used).

[0013] The duplexer 40 includes an input terminal 64 to receive acontrol signal PAon that is high whenever the power amplifier 52 isactive and low at all other times. The input terminal 64 is connected tothe gate terminals of three n-type metal oxide semiconductor (NMOS)transistor switches (M₁, M₂, and M₃) 66, 68, 70 within the duplexer 40.The input terminal 64 is also connected to the gate terminals of twop-type metal oxide semiconductor (PMOS) transistor switches (M₉ and M₁₀)66, 68, 70 through an inverter 86. The PAon signal is also delivered toa disable transistor (M₈) 76 within the LNA 50 to deactivate the LNA 50when the power amplifier 52 is active. In the illustrated embodiment,this is achieved by shorting the bias to the first stage current sourcewithin the LNA 50 when PAon is high. As illustrated, the first receiverterminal 42 is connected to the first antenna terminal 56 through afirst inductor (L₁) 72 and the second receiver terminal 44 is connectedto the second antenna terminal 58 through a second inductor (L₂) 74. Thefirst NMOS transistor 66 is connected at one source/drain terminal to afirst capacitor (C₁) 78 and at the other source/drain terminal to asecond capacitor (C₂) 80. The first and second capacitors 78, 80 areeach coupled at another end to the first and second antenna terminals56, 58, respectively. The second NMOS transistor 68 and the first PMOStransistor 82 are each connected at one source/drain terminal to thefirst transmitter terminal 46 and at the other source/drain terminal tothe first receiver terminal 42. Similarly, the third NMOS transistor 70and the second PMOS transistor 84 are each connected at one source/drainterminal to the second transmitter terminal 48 and at the othersource/drain terminal to the second receiver terminal 44.

[0014] As discussed above, when the power amplifier 52 is active, thePAon signal is logic high. Thus, the first, second, and third NMOStransistors 66, 68, 70 and the first and second PMOS transistors 82, 84are turned “on.” The second NMOS transistor 68 and the first PMOStransistor 82 act collectively as a pass gate for coupling the firsttransmitter terminal 46 to the first receiver terminal 42 when the PAonsignal is logic high. Similarly, the third NMOS transistor 70 and thesecond PMOS transistor 84 act collectively as a pass gate for couplingthe second transmitter terminal 48 to the second receiver terminal 44when the PAon signal is logic high. In addition, the first NMOStransistor 66 appears as a very low impedance (e.g., a short circuit)between the first and the second capacitors 76, 78 when the PAon signalis high. Therefore, during a transmit operation, the power amplifier 52is coupled to the antenna 54 through an LC network consisting of thefirst and second series inductors 72, 74 and the first and second shuntcapacitors 78, 80. The inductance value of the first and secondinductors 72, 74 and capacitance value of the first and secondcapacitors 76, 78 are selected so that the resulting LC configurationmatches the output impedance of the power amplifier 52 to the antennaimpedance at the antenna terminals 56, 58 (i.e., using an L matcharrangement). Importantly, the LC configuration also behaves as animpedance transformation between the antenna terminals 56, 58 and thereceiver terminals 42, 44 to transform the antenna impedance at theantenna terminals 56, 58 to a relatively low impedance at the receiverterminals 42, 44. It should be appreciated that other circuitconfigurations for performing this matching/impedance transformationfunction are also possible, including, for example, the well known πmatch circuit. Methods for designing such circuits are well known in theart.

[0015] Because the impedance is low at the receiver terminals 42, 44during transmit, the transmit signal being generated by the poweramplifier 52 will maintain a relatively low voltage swing at thereceiver terminals 42, 44. In accordance with the invention, thetransmit voltage swing at the receiver terminals 42, 44 will be keptbelow a value that could potentially damage the input devices M₄ and M₅(or other circuitry) within the LNA 50. Because the impedance at thereceiver terminals 42, 44 is low, the currents being developed at thefirst and second transmitter terminals 46, 48 will be relatively high.However, because the input impedance of the LNA 50 is high, this currentwill not flow into or damage the LNA 50. The second and third NMOStransistors 68, 70 and the first and second PMOS transistors 82, 84, onthe other hand, must be designed to handle this current load. Thetransmit signal generated by the power amplifier 52 will be transformedby the action of the LC configuration into a relatively high voltageswing signal at the antenna terminals 56, 58. Thus, the signaltransmitted by the antenna 62 will have sufficient power to reach aremote transceiver with adequate signal level. Although the voltageswing on the antenna terminals 56, 58 will be relatively high, the firsttransistor switch 66 will not be damaged because it is located at a lowvoltage virtual ground between the antenna terminals 56, 58.

[0016] When the PAon signal goes low, the first, second, and third NMOStransistors 66, 68, 70 and the first and second PMOS transistors 82, 84within the duplexer 40 are turned “off.” In addition, the disabletransistor 76 within the LNA 50 is turned “off,” thus enabling the LNA50. The first and second transmitter terminals 46, 48 are now isolatedfrom the first and second receiver terminals 42,44, respectively.Furthermore, the first NMOS transistor 66 now appears as an open circuitbetween the first and second capacitors 78, 80, effectively removing thecapacitors 78, 80 from the circuit. In this mode, the first and secondinductors 72, 74 are used as matching elements to match the antennaimpedance at the antenna terminals 56, 58 to the input impedance of theLNA 50. In one approach, the parasitic capacitances of the second andthird NMOS transistors 68, 70 and the first and second PMOS transistors82, 84 (in the “off” state) are used as additional tuning elements tomatch the antenna 62 to the LNA 50. Transistor design methods forachieving a desired parasitic capacitance at the appropriate terminalsof the second and third transistor switches 68, 70 for a given set ofbias conditions are known in the art.

[0017] The selection of the inductance value of the first and secondinductors 72, 74 and the capacitance value of the first and secondcapacitances 78, 80 (and, if used, the parasitic capacitance value ofthe second and third NMOS transistors 68, 70 and the first and secondPMOS transistors 82, 84 in the “off” state) is preferably performed aspart of a single design process to achieve the dual goals of providingtransformer action during transmit and impedance matching duringreceive. Techniques for accomplishing this are well known in the art andnormally involve the use of computer based circuit design and analysistools. The design may require that some additional matching circuitry beimplemented within the LNA 50 and/or the power amplifier 52 to interactwith the circuit elements within the duplexer 40 during receive and/ortransmit mode to adequately match the antenna 62 to the LNA 50 and thepower amplifier 52. The actual design that is implemented will dependupon the intrinsic input impedances of the LNA 50 and the poweramplifier 52 before impedance matching/transformation is undertaken. Itshould be appreciated that the particular arrangement of inductances andcapacitances within the duplexer 40 of FIG. 3 is merely an illustrationof one possible approach. As will be apparent to a person of ordinaryskill in the art, many alternative circuit element configurations can beimplemented to achieve the dual goals of providing transformer actionduring transmit and impedance matching during receive.

[0018] In the illustrated embodiment, the three NMOS transistors 66, 68,70 and the two PMOS transistors 82, 84 are metal-oxide-semiconductorfield effect transistors (MOSFETs). This allows the duplexer 40 to beeasily integrated within a CMOS environment. It should be appreciated,however, that other transistor types can also be used in accordance withthe present invention, such as other insulated-gate FET structures,bipolar junction transistors, junction FETs, and others. In oneembodiment of the invention, the duplexer 40 of FIG. 3 is implementedwithout the second and third NMOS transistors 68, 70 and the first andsecond PMOS transistors 82, 84. In this embodiment, the first and secondtransmitter terminals 46, 48 are connected directly to the first andsecond receiver terminals 42, 44, respectively. Using well known RFtechniques, the length of the lines coupling the transmitter terminals46, 48 to the receiver terminals 42, 44 can be adapted to provide aminimal impedance effect (e.g., an open circuit) at the receiver inputterminals 42, 44 during receive mode.

[0019] Using the duplexer 40 of FIG. 3, it is possible to connectmultiple transceivers to a single antenna 62, as long as only onetransceiver is allowed to operate at any given time. In one approach,multiple power amplifiers 52 are connected to the transmitter terminals46, 48 in parallel and multiple LNAs 50 are connected to the receiverterminals 42, 44 in parallel. The PAon signal is high if any of thepower amplifiers 52 are enabled. As long as only a single poweramplifier 52 or a single LNA 50 is operative at a time, the duplexer 40will operate in substantially the same manner described above.Alternatively, additional transistor switches can be provided at thetransmitter terminals 46, 48 and/or the receiver terminals 42, 44 toswitch between the multiple transceivers in response to a controlsignal. This technique provides greater isolation between individualtransceivers, but adds complexity to the duplexer 40. Othermulti-transceiver topologies are also possible. In particular,simultaneous operation of multiple transceivers can be enabled if thetransceivers each operate at frequency multiples of one another suchthat the transmission lines connecting each transceiver to the antennaappear as open circuits to the other transceivers.

[0020] With reference to FIG. 3, in one aspect of the present invention,the duplexer 40, the LNA 50, and the power amplifier 52 are allintegrated on the same semiconductor chip. In one embodiment, very largescale integration (VLSI) techniques are used to integrate the elements.Preferably, the elements will be integrated using well known CMOStechniques, although other processes are also possible. Additionalelements within the receiver and transmitter circuits (i.e., other thanthe LNA 50 and power amp 52, respectively) can also be integrated on thechip. In one embodiment, for example, an entire transceiver subsystemincluding receiver, transmitter, duplexer, and digital circuitry forcontrol and/or signal processing is integrated onto a single chip. Thechip will preferably be housed within an integrated circuit package foreasy mounting on a circuit board or the like. The circuit board may thenbe coupled to an antenna, either with or without an intervening balunstructure (depending on the type of antenna used). In one approach, abalun is implemented on the semiconductor chip with the other circuitry.

[0021] Although the present invention has been described in conjunctionwith certain embodiments, it is to be understood that modifications andvariations may be resorted to without departing from the spirit andscope of the invention as those skilled in the art readily understand.Such modifications and variations are considered to be within thepurview and scope of the invention and the appended claims.

1-26. (Canceled)
 27. A method of operating a duplexer comprising:transforming an impedance of an antenna with a reconfigurable networkcomprising an inductor and a capacitor coupled between a transmitter, areceiver, and the antenna to support signal transmission from theantenna; and matching the impedance of the antenna to an input impedanceof the receiver by removing the capacitor from the reconfigurablenetwork to support signal reception through the antenna.
 28. The methodof claim 27 wherein transforming an impedance of an antenna furthercomprises transforming the impedance of the antenna to a lower impedanceat the receiver with the reconfigurable network.
 29. The method of claim27, further comprising switching between matching the impedance of theantenna and transforming an impedance of an antenna with a switch in thereconfigurable network.
 30. The method of claim 29 wherein switchingfurther comprises: switching off a transistor coupled between a firstcapacitor and a second capacitor to remove the first capacitor and thesecond capacitor from the reconfigurable network; and isolating thetransmitter from the receiver.
 31. The method of claim 27, furthercomprising coupling the transmitter to the receiver through at least onepass gate comprising an NMOS transistor and a PMOS transistor inresponse to a control signal.
 32. The method of claim 27 wherein:transforming an impedance of an antenna further comprises transformingthe impedance of the antenna to support differential signal transmissionthrough the reconfigurable network; and matching the impedance of theantenna further comprises matching the impedance of the antenna tosupport differential signal transmission through the reconfigurablenetwork.
 33. A method of transmitting and receiving signals comprising:generating an outgoing signal in a transmitter; transmitting a signalfrom an antenna coupled to the transmitter based on the outgoing signal;transforming an impedance of the antenna with a reconfigurable networkcomprising an inductor and a capacitor coupled between the antenna, thetransmitter, and a receiver when a signal is being transmitted from theantenna; receiving a signal at the antenna; coupling an incoming signalto the receiver through the reconfigurable network based on the signalreceived by the antenna; and matching the impedance of the antenna to aninput impedance of the receiver by removing the capacitor from thereconfigurable network when the receiver is receiving the incomingsignal.
 34. The method of claim 33 wherein transforming an impedance ofthe antenna further comprises transforming an impedance of the antennato a lower impedance at the receiver with the reconfigurable network.35. The method of claim 33, further comprising switching betweenmatching the impedance of the antenna and transforming an impedance ofthe antenna with a switch in the reconfigurable network.
 36. The methodof claim 35 wherein switching further comprises: switching off atransistor coupled between a first capacitor and a second capacitor toremove the first capacitor and the second capacitor from thereconfigurable network; and isolating the transmitter from the receiver.37. The method of claim 33 wherein: generating an outgoing signal in atransmitter further comprises generating a differential outgoing signalin the transmitter; and coupling an incoming signal to the receiverfurther comprises coupling a differential incoming signal to thereceiver.
 38. The method of claim 33, further comprising processing theincoming signal coupled to the receiver with signal processingcircuitry.
 39. The method of claim 33, further comprising coupling thetransmitter to the receiver through at least one pass gate comprising anNMOS transistor and a PMOS transistor in response to a control signal.40. The method of claim 39 wherein generating an outgoing signal in atransmitter further comprises amplifying the outgoing signal in a poweramplifier coupled to the receiver and the reconfigurable network throughthe at least one pass gate.
 41. A method of transmitting and receivingsignals comprising: generating a differential outgoing signal in atransmitter; transmitting a signal from an antenna coupled to thetransmitter based on the differential outgoing signal; transforming animpedance of the antenna with a duplexer when a signal is beingtransmitted from the antenna, the duplexer comprising a first inductorand a first capacitor coupled to a first terminal of the antenna and asecond inductor and a second capacitor coupled to a second terminal ofthe antenna, the duplexer being coupled between the first terminal andthe second terminal of the antenna, differential terminals of thetransmitter, and differential terminals of a receiver; receiving asignal at the antenna; coupling a differential incoming signal to thedifferential terminals of the receiver through the duplexer based on thesignal received by the antenna; and matching the impedance of theantenna to an input impedance of the receiver by removing the firstcapacitor and the second capacitor from the duplexer when the receiveris receiving the differential incoming signal.
 42. The method of claim41 wherein transforming an impedance of the antenna further comprisestransforming an impedance of the antenna to a lower impedance at thedifferential terminals of the receiver with the duplexer.
 43. The methodof claim 41, further comprising switching between matching the impedanceof the antenna and transforming an impedance of the antenna with aswitch in the duplexer.
 44. The method of claim 43 wherein switchingfurther comprises: switching off a transistor coupled between the firstcapacitor and the second capacitor to remove the first capacitor and thesecond capacitor from the duplexer; and isolating the transmitter fromthe receiver.
 45. The method of claim 41, further comprising processingthe differential incoming signal coupled to the differential terminalsof the receiver with signal processing circuitry.
 46. The method ofclaim 41, further comprising coupling the transmitter to the receiverthrough a first pass gate coupled between a first terminal of thereceiver and a first terminal of the transmitter and a second pass gatecoupled between a second terminal of the receiver and a second terminalof the transmitter in response to a control signal, each of the firstpass gate and the second pass gate comprising an NMOS transistor and aPMOS transistor.
 47. The method of claim 46 wherein generating adifferential outgoing signal in a transmitter further comprisesamplifying the differential outgoing signal in a power amplifier coupledto the receiver and the duplexer through the first pass gate and thesecond pass gate.
 48. A transceiver comprising: an antenna coupled to abalun; a duplexer comprising first and second balun terminals coupled tothe balun; a differential receiver coupled to first and second receiverterminals of the duplexer; and a differential transmitter coupled tofirst and second transmitter terminals of the duplexer, the duplexercomprising first and second capacitors coupled between first and secondinductors and the first and second balun terminals, the duplexer beingcoupled between the balun, the differential receiver, and thedifferential transmitter, the first and second capacitors and the firstand second inductors comprising an impedance transformation circuitbetween the first and second balun terminals and the differentialtransmitter when a signal is being transmitted from the antenna, and thefirst and second inductors with the first and second capacitors removedfrom the duplexer comprising an impedance matching circuit between thefirst and second balun terminals and the differential receiver when asignal is being coupled to the differential receiver.
 49. Thetransceiver of claim 48, further comprising: a first pass gatecomprising a PMOS device and an NMOS device coupled between the firstreceiver terminal and the first transmitter terminal; and a second passgate comprising a PMOS device and an NMOS device coupled between thesecond receiver terminal and the second transmitter terminal.
 50. Thetransceiver of claim 48 wherein: the first receiver terminal and thefirst transmitter terminal are coupled to the first inductor; and thesecond receiver terminal and the second transmitter terminal are coupledto the second inductor.
 51. The transceiver of claim 48, furthercomprising a switch coupled between the first capacitor and the secondcapacitor and a control signal to couple the first capacitor to thesecond capacitor in response to the control signal when a signal isbeing transmitted from the antenna and to decouple the first capacitorfrom the second capacitor in response to the control signal to removethe first and second capacitors from the duplexer when a signal is beingcoupled to the differential receiver.
 52. The transceiver of claim 51wherein the switch comprises a transistor comprising a first terminalcoupled to a plate of the first capacitor, a second terminal coupled toa plate of the second capacitor, and a control terminal coupled toreceive the control signal.
 53. The transceiver of claim 48 wherein thedifferential transmitter further comprises a power amplifier coupled tothe first and second transmitter terminals.
 54. The transceiver of claim48 wherein the differential transmitter, the differential receiver, andthe duplexer comprise circuit elements on a common semiconductor chip.55. The transceiver of claim 54, further comprising: digital controlcircuitry in the common semiconductor chip to control the differentialtransmitter, the differential receiver, and the duplexer; and signalprocessing circuitry in the common semiconductor chip to process thesignal coupled to the differential receiver.